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1550 MHz to 2150 MHz Rx Mixer with Integrated Fractional-N PLL and VCO ADRF6602
FEATURES
Rx mixer with integrated fractional-N PLL RF input frequency range: 1000 MHz to 3100 MHz Internal LO frequency range: 1550 MHz to 2150 MHz Input P1dB: 14.5 dBm Input IP3: 30 dBm IIP3 optimization via external pin SSB noise figure IP3SET pin open: 13.5 dB IP3SET pin at 3.3 V: 14 dB Voltage conversion gain: 6 dB Matched 200 IF output impedance IF 3 dB bandwidth: 500 MHz Programmable via 3-wire SPI interface 40-lead, 6 mm x 6 mm LFCSP
GENERAL DESCRIPTION
The ADRF6602 is a high dynamic range active mixer with integrated phase-locked loop (PLL) and voltage-controlled oscillator (VCO). The PLL/synthesizer uses a fractional-N PLL to generate an fLO input to the mixer. The reference input can be divided or multiplied and then applied to the PLL phase frequency detector (PFD). The PLL can support input reference frequencies from 12 MHz to 160 MHz. The PFD output controls a charge pump whose output drives an off-chip loop filter. The loop filter output is then applied to an integrated VCO. The VCO output at 2x fLO is applied to an LO divider, as well as to a programmable PLL divider. The programmable PLL divider is controlled by a - modulator (SDM). The modulus of the SDM can be programmed from 1 to 2047. The active mixer converts the single-ended 50 RF input to a 200 differential IF output. The IF output can operate up to 500 MHz. The ADRF6602 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, RoHS-compliant, 6 mm x 6 mm LFCSP with an exposed paddle. Performance is specified over the -40C to +85C temperature range.
APPLICATIONS
Cellular base stations
FUNCTIONAL BLOCK DIAGRAM
VCC1
1
VCC2
10
VCC_LO
17
VCC_MIX
22
VCC_V2I
27
VCC_LO
34
NC NC
32 33
ADRF6602
LODRV_EN 36 LON 37
BUFFER
INTERNAL LO RANGE 1550MHz TO 2150MHz
3.3V LDO 2.5V LDO
2
DECL3P3 DECL2P5
LOP 38 PLL_EN 16 DATA 12 CLK 13 LE 14 SPI INTERFACE FRACTION MODULUS REG THIRD-ORDER FRACTIONAL INTERPOLATOR x2 REF_IN 6 /2 /4 MUXOUT 8
4 7 11 15 20 21 23 24 25 28 30 31 35 BUFFER
9
INTEGER REG
2:1 MUX
DIV BY 4, 2, 1
VCO LDO
40 DECLVCO
26 RF IN
N COUNTER 21 TO 123 MUX TEMP SENSOR - PHASE + FREQUENCY DETECTOR
PRESCALER /2 CHARGE PUMP 250A, 500A (DEFAULT), 750A, 1000A
5 3
VCO CORE
29 IP3SET
39
18 19
GND
RSET
CP VTUNE IFP IFN
Figure 1.
Rev. 0
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08545-001
ADRF6602 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 RF Specifications .......................................................................... 3 Synthesizer/PLL Specifications ................................................... 4 Logic Input and Power Specifications ....................................... 5 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 9 Register Structure ........................................................................... 11 Register 0--Integer Divide Control (Default: 0x0001C0)..... 11 Register 1--Modulus Divide Control (Default: 0x003001) .. 11 Register 2--Fractional Divide Control (Default: 0x001802) .................................................................................... 12 Register 3--- Modulator Dither Control (Default: 0x10000B) .................................................................................... 12 Register 4--PLL Charge Pump, PFD, and Reference Path Control (Default: 0x0AA7E4)................................................... 13 Register 5--PLL Enable and LO Path Control (Default: 0x0000E5) .................................................................................... 14 Register 6--VCO Control and VCO Enable (Default: 0x1E2106) .................................................................................... 14 Register 7--Mixer Bias Enable and External VCO Enable (Default: 0x000007).................................................................... 14 Theory of Operation ...................................................................... 15 Programming the ADRF6602................................................... 15 Initialization Sequence .............................................................. 15 LO Selection Logic ..................................................................... 16 Applications Information .............................................................. 17 Basic Connections for Operation ............................................. 17 Evaluation Board ............................................................................ 18 Evaluation Board Control Software ......................................... 18 Schematics and Artwork ........................................................... 20 Evaluation Board Configuration Options ............................... 22 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23
REVISION HISTORY
1/10--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADRF6602 SPECIFICATIONS
RF SPECIFICATIONS
VS = 5 V; ambient temperature (TA) = 25C; fREF = 38.4 MHz; fPFD = 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized using capacitor DAC (0x0) and IP3SET (3.3 V), unless otherwise noted. Table 1.
Parameter INTERNAL LO FREQUENCY RANGE RF INPUT FREQUENCY RANGE RF INPUT AT 1410 MHz Input Return Loss Input P1dB Second-Order Intercept (IIP2) Third-Order Intercept (IIP3) Single-Side Band Noise Figure LO to IF Leakage RF INPUT AT 1760 MHz Input Return Loss Input P1dB Second-Order Intercept (IIP2) Third-Order Intercept (IIP3) Single-Side Band Noise Figure LO to IF Leakage RF INPUT AT 2010 MHz Input Return Loss Input P1dB Second-Order Intercept (IIP2) Third-Order Intercept (IIP3) Single-Side Band Noise Figure LO to IF Leakage IF OUTPUT Voltage Conversion Gain IF Bandwidth Output Common-Mode Voltage Gain Flatness Gain Variation Output Swing Output Return Loss LO INPUT/OUTPUT (LOP, LON) Frequency Range Output Level (LO as Output) Input Level (LO as Input) Input Impedance Test Conditions/Comments 3 dB RF input range Relative to 50 (can be improved with external match) -5 dBm each tone (10 MHz spacing between tones) -5 dBm each tone (10 MHz spacing between tones) IP3SET = 3.3 V IP3SET = open At 1x LO frequency, 50 termination at the RF port Relative to 50 (can be improved with external match) -5 dBm each tone (10 MHz spacing between tones) -5 dBm each tone (10 MHz spacing between tones) IP3SET = 3.3 V IP3SET = open At 1x LO frequency, 50 termination at the RF port Relative to 50 (can be improved with external match) -5 dBm each tone (10 MHz spacing between tones) -5 dBm each tone (10 MHz spacing between tones) IP3SET = 3.3 V IP3SET = open At 1x LO frequency, 50 termination at the RF port Differential 200 load Small-signal 3 dB bandwidth External pull-up balun or inductors required Over frequency range, any 5 MHz/50 MHz Over full temperature range Differential 200 load Relative to 200 Externally applied 1x LO input, internal PLL disabled 250 1x LO into a 50 load, LO output buffer enabled -7 6 50 Min 1550 1000 Typ Max 2150 3100 Unit MHz MHz dB dBm dBm dBm dB dB dBm dB dBm dBm dBm dB dB dBm dB dBm dBm dBm dB dB dBm dB MHz V dB dB V p-p dB 6000 MHz dBm dBm
-12 15 56.5 31.5 14 13.5 -47 -12 15 55 30.0 15 13.3 -47 -12 14.5 57 28.5 16 14.7 -46 6 500 5 0.2/1.0 1.0 2 -12
Rev. 0 | Page 3 of 24
ADRF6602
SYNTHESIZER/PLL SPECIFICATIONS
VS = 5 V; ambient temperature (TA) = 25C; fREF = 153.6 MHz; fPFD = 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized using capacitor DAC (0x0) and IP3SET (3.3 V), unless otherwise noted. Table 2.
Parameter SYNTHESIZER SPECIFICATIONS Frequency Range Figure of Merit Reference Spurs Test Conditions/Comments Synthesizer specifications referenced to 1x LO Internally generated LO PREF_IN = 0 dBm fREF = 153.6 MHz fREF/4 fREF/2 fREF > fREF fLO = 1550 MHz to 2150 MHz, fPFD = 38.4 MHz 1 kHz to 10 kHz offset 100 kHz offset 500 kHz offset 1 MHz offset 5 MHz offset 10 MHz offset 20 MHz offset 1 kHz to 40 MHz integration bandwidth REF_IN, MUXOUT pins 12 4 VOL (lock detect output selected) VOH (lock detect output selected) 0.25 2.7 50 Programmable to 250 A, 500 A, 750 A, 1 mA 1 500 2.8 160 MHz pF V V % A V Min 1550 -222 -105 -105 -80 -85 -90 -103 -122 -130 -142 -148 -150 0.3 20 40 Typ Max 2150 Unit MHz dBc/Hz dBc dBc dBc dBc dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz rms MHz
PHASE NOISE
Integrated Phase Noise PFD Frequency REFERENCE CHARACTERISTICS REF_IN Input Frequency REF_IN Input Capacitance MUXOUT Output Level MUXOUT Duty Cycle CHARGE PUMP Pump Current Output Compliance Range
Rev. 0 | Page 4 of 24
ADRF6602
LOGIC INPUT AND POWER SPECIFICATIONS
VS = 5 V; ambient temperature (TA) = 25C; fREF = 38.4 MHz; fPFD = 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized using capacitor DAC (0x0) and IP3SET (3.3 V), unless otherwise noted. Table 3.
Parameter LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN POWER SUPPLIES Voltage Range Supply Current Test Conditions/Comments CLK, DATA, LE Min 1.4 0 0.1 5 VCC1, VCC2, VCC_LO, VCC_MIX, and VCC_V2I pins 4.75 PLL only External LO mode (internal PLL disabled, IP3SET pin = 3.3 V) Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V) Power-down mode 5 97 165 262 30 5.25 V mA mA mA mA Typ Max 3.3 0.7 Unit V V A pF
TIMING CHARACTERISTICS
VCC2 = 5 V 5%. Table 4.
Parameter t1 t2 t3 t4 t5 t6 t7 Limit 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min Description LE setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width
Timing Diagram
t4
CLK
t5
t2
DATA DB23 (MSB) DB22
t3
DB2 (CONTROL BIT C3) DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)
t1
LE
t6
t7
08545-002
Figure 2. Timing Diagram
Rev. 0 | Page 5 of 24
ADRF6602 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Supply Voltage, VCC1, VCC2, VCC_LO, VCC_MIX, VCC_V2I Digital I/O, CLK, DATA, LE IFP, IFN RFIN JA (Exposed Paddle Soldered Down) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating -0.5 V to +5.5 V -0.3 V to +3.6 V -0.3 V to VCC + 0.3 V 18 dBm 35C/W 150C -40C to +85C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 6 of 24
ADRF6602 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
40 39 38 37 36 35 34 33 32 31 DECLVCO VTUNE LOP LON LODRV_EN GND VCC_LO NC NC GND
VCC1 1 DECL3P3 2 CP 3 GND 4 RSET 5 REF_IN 6 GND 7 MUXOUT 8 DECL2P5 9 VCC2 10
PIN 1 INDICATOR
ADRF6602
TOP VIEW (Not to Scale)
30 29 28 27 26 25 24 23 22 21
GND IP3SET GND VCC_V2I RFIN GND GND GND VCC_MIX GND
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1 2 3 4, 7, 11, 15, 20, 21, 23, 24, 25, 28, 30, 31, 35 5 Mnemonic VCC1 DECL3P3 CP GND Description Power Supply for the 3.3 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 F capacitor located close to the pin. Decoupling Node for 3.3 V LDO. Connect a 0.1 F capacitor between this pin and ground. Charge Pump Output Pin. Connect to VTUNE through loop filter. Ground. Connect these pins to a low impedance ground plane.
RSET
Charge Pump Current. The nominal charge pump current can be set to 250 A, 500 A, 750 A, or 1 mA using Bit DB11 and Bit DB10 in Register 4 and by setting Bit DB18 to 0 (internal reference current). In this mode, no external RSET is required. If Bit DB18 is set to 1, the four nominal charge pump currents (INOMINAL) can be externally adjusted according to the following equation:
217.4 x I CP R SET = I NOMINAL
6 8 9 10 12 13 14 16 REF_IN MUXOUT DECL2P5 VCC2 DATA CLK LE PLL_EN
- 37.8
17, 34 18, 19 22 26
VCC_LO IFP, IFN VCC_MIX RFIN
Reference Input. Nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz. Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect signal. The output is selected by programming the appropriate register. Decoupling Node for 2.5 V LDO. Connect a 0.1 F capacitor between this pin and ground. Power Supply for the 2.5 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 F capacitor located close to the pin. Serial Data Input. The serial data input is loaded MSB first; the three LSBs are the control bits. Serial Clock Input. The serial clock input is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz. Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the eight registers. The relevant latch is selected by the three control bits of the 24-bit word. PLL Enable. Switch between internal PLL and external LO input. When this pin is logic high, the mixer LO is automatically switched to the internal PLL and the internal PLL is powered up. When this pin is logic low, the internal PLL is powered down and the external LO input is routed to the mixer LO inputs. The SPI can also be used to switch modes. Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 F capacitor located close to the pin. Mixer IF Outputs. These outputs should be pulled to VCC with RF chokes. Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 F capacitor located close to the pin. RF Input (Single-Ended, 50 ).
Rev. 0 | Page 7 of 24
08545-003
NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A LOW IMPEDANCE GROUND PLANE.
GND DATA CLK LE GND PLL_EN VCC_LO IFP IFN GND
11 12 13 14 15 16 17 18 19 20
ADRF6602
Pin No. 27 29 32, 33 36 Mnemonic VCC_V2I IP3SET NC LODRV_EN Description Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 F capacitor located close to the pin. Connect a resistor from this pin to a +5 V supply to adjust IIP3. Normally leave open. No Connection. LO Driver Enable. Together with Pin 16 (PLL_EN), this digital input pin determines whether the LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the PLL_EN pin is low or if the PLL_EN pin is set high with the PLEN bit (DB6 in Register 5) set to 0. LOP and LON become outputs if either the LODRV_EN pin or the LDRV bit (DB3 in Register 5) is set to 1 while the PLL_EN pin is set high. External LO drive frequency must be 1x LO. This pin should not be left floating. Local Oscillator Input/Output. The internally generated 1x LO is available on these pins. When internal LO generation is disabled, an external 1x LO can be applied to these pins. VCO Control Voltage Input. This pin is driven by the output of the loop filter. Nominal input voltage range on this pin is 1.5 V to 2.5 V. Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 F capacitor between this pin and ground. Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.
37, 38 39 40 EP
LON, LOP VTUNE DECLVCO EPAD
Rev. 0 | Page 8 of 24
ADRF6602 TYPICAL PERFORMANCE CHARACTERISTICS
CDAC = 0x0, IP3SET = 3.3 V, internally generated LO, RFIN = -10 dBm, fIF = 140 MHz, unless otherwise noted.
5 4 3
35 45 40
2
INPUT IP3 (dBm)
GAIN (dB)
1 0 -1 -2
-40C +25C +85C
+85C 30 -40C +25C 25 20 15
-3 -4 1650 1750 1850 1950 2050 2150
08545-014
10
08545-017
08545-019 08545-018
-5 1550
5 1550
1650
1750
1850
1950
2050
2150
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 4. Gain vs. LO Frequency
Figure 7. IIP3 vs. LO Frequency, RFIN = -5 dBm
90
20 18
80
16 14 12 10 8 6 4 2
+25C +85C -40C
+85C 60
+25C
50
-40C
40
1650
1750
1850
1950
2050
2150
08545-015
30 1550
INPUT P1dB (dBm)
INPUT IP2 (dBm)
70
0 1550
1650
1750
1850
1950
2050
2150
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 5. IIP2 vs. LO Frequency, RFIN = -5 dBm
Figure 8. IP1dB vs. LO Frequency
20
0 -5
LO FEEDTHROUGH AMPLITUDE (dBm)
19 18
-10 -15 -20 -25 -30 -35 -40 -45 -50 -55 +25C -40C +85C
NOISE FIGURE (dB)
17 16 15
+85C
14 13
+25C
-40C
12 11
08545-016
10 1550
1650
1750
1850
1950
2050
2150
-60 1550
1650
1750
1850
1950
2050
2150
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 6. Noise Figure vs. LO Frequency
Figure 9. LO Feedthrough to IF vs. LO Frequency, LO Output Turned Off
Rev. 0 | Page 9 of 24
ADRF6602
Phase noise measurements made at LO output, unless otherwise noted.
-80 -90
SPOT PHASE NOISE (dBc/Hz)
1.0 0.9
INTEGRATED PHASE NOISE (rms)
-80 -90 LO = 2134.4MHz -100 -110 -120 -130 -140 -150 -160 1k LO = 1558.4MHz
1kHz OFFSET
0.8 -100 -110
10kHz OFFSET 100kHz OFFSET
0.7 0.6 0.5
-120
1MHz OFFSET
-130
INTERGRATED PHASE NOISE
0.4 0.3 0.2 0.1
-140
10MHz OFFSET
-150 -160 1550
08545-020
1650
1750
1850
1950
2050
10k
100k
1M
10M
100M
LO FREQUENCY (MHz)
OFFSET FREQUENCY (Hz)
Figure 10. PLL Spot Phase Noise at Various Offsets and Integrated Phase Noise vs. LO Frequency
Figure 12. Phase Noise vs. Offset Frequency and LO Frequency (LO Frequency Varies from 1550 MHz to 2150 MHz)
-70 -75 1x PFD OFFSET -80
SPURS LEVEL (dBc)
-85 2x PFD OFFSET -90 -95 -100 -105 -110 1550
0.25x AND 0.5x PFD OFFSET
4x PFD OFFSET
1650
1750
1850
1950
2050
2150
LO FREQUENCY (MHz)
Figure 11. PLL Reference Spurs vs. LO Frequency
Rev. 0 | Page 10 of 24
08545-021
08545-022
0 2150
PHASE NOISE (dBc/Hz)
ADRF6602 REGISTER STRUCTURE
This section provides the register maps for the ADRF6602. The three LSBs determine the register that is programmed.
REGISTER 0--INTEGER DIVIDE CONTROL (DEFAULT: 0x0001C0)
RESERVED DB23 0 DB22 0 DB21 0 DB20 0 DB19 0 DB18 0 DB17 0 DB16 0 DB15 0 DB14 0 DB13 0 DB12 0 DB11 0 DIVIDE MODE DB10 DM DB9 ID6 DB8 ID5 INTEGER DIVIDE RATIO DB7 ID4 DB6 ID3 DB5 ID2 DB4 ID1 DB3 ID0 CONTROL BITS DB2 C3(0) DB1 C2(0) DB0 C1(0)
DM 0 1
DIVIDE MODE FRACTIONAL (DEFAULT) INTEGER
ID6 0 0 0 0 ... ... 0 ... ... 1 1 1 1 1
ID5 0 0 0 0 ... ... 1 ... ... 1 1 1 1 1
ID4 1 1 1 1 ... ... 1 ... ... 1 1 1 1 1
ID3 0 0 0 1 ... ... 1 ... ... 0 1 1 1 1
ID2 1 1 1 0 ... ... 0 ... ... 1 0 0 0 0
ID1 0 1 1 0 ... ... 0 ... ... 1 0 0 1 1
ID0 1 0 1 0 ... ... 0 ... ... 1 0 1 0 1
INTEGER DIVIDE RATIO 21 (INTEGER MODE ONLY) 22 (INTEGER MODE ONLY) 23 (INTEGER MODE ONLY) 24 ... ... 56 (DEFAULT) ... ... 119 120 (INTEGER MODE ONLY) 121 (INTEGER MODE ONLY)
08545-004
122 (INTEGER MODE ONLY) 123 (INTEGER MODE ONLY)
Figure 13. Register 0--Integer Divide Control Register Map
REGISTER 1--MODULUS DIVIDE CONTROL (DEFAULT: 0x003001)
RESERVED DB23 DB22 0 0 DB21 0 DB20 0 DB19 0 DB18 0 DB17 0 DB16 0 DB15 0 DB14 0 DB13 MD10 DB12 MD9 DB11 MD8 DB10 MD7 MODULUS VALUE DB9 MD6 DB8 MD5 DB7 MD4 DB6 MD3 DB5 MD2 DB4 MD1 DB3 MD0 CONTROL BITS DB2 C3(0) DB1 C2(0) DB0 C1(1)
MD10 0 0 ... ... 1 ... ... 1
MD9 0 0 ... ... 1 ... ... 1
MD8 0 0 ... ... 0 ... ... 1
MD7 0 0 ... ... 0 ... ... 1
MD6 0 0 ... ... 0 ... ... 1
MD5 0 0 ... ... 0 ... ... 1
MD4 0 0 ... ... 0 ... ... 1
MD3 0 0 ... ... 0 ... ... 1
MD2 0 0 ... ... 0 ... ... 1
MD1 0 1 ... ... 0 ... ... 1
MD0 1 0 ... ... 0 ... ... 1
MODULUS VALUE 1 2 ... ... 1536 (DEFAULT) ... ... 2047
08545-005
Figure 14. Register 1--Modulus Divide Control Register Map
Rev. 0 | Page 11 of 24
ADRF6602
REGISTER 2--FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x001802)
RESERVED DB23 0 DB22 0 DB21 0 DB20 0 DB19 0 DB18 0 DB17 0 DB16 0 DB15 0 DB14 0 DB13 FD10 DB12 FD9 DB11 FD8 DB10 FD7 FRACTIONAL VALUE DB9 FD6 DB8 FD5 DB7 FD4 DB6 FD3 DB5 FD2 DB4 FD1 DB3 FD0 CONTROL BITS DB2 C3(0) DB1 C2(1) DB0 C1(0)
FD10 0 0 ... ... 0 ... ...
FD9 0 0 ... ... 1 ... ...
FD8 0 0 ... ... 1 ... ...
FD7 0 0 ... ... 0 ... ...
FD6 0 0 ... ... 0 ... ...
FD5 0 0 ... ... 0 ... ...
FD4 0 0 ... ... 0 ... ...
FD3 0 0 ... ... 0 ... ...
FD2 0 0 ... ... 0 ... ...
FD1 0 0 ... ... 0 ... ...
FD0 0 1 ... ... 0 ... ...
FRACTIONAL VALUE 0 1 ... ... 768 (DEFAULT) ... ... 08545-006
08545-007
FRACTIONAL VALUE MUST BE LESS THAN MODULUS
Figure 15. Register 2--Fractional Divide Control Register Map
REGISTER 3--- MODULATOR DITHER CONTROL (DEFAULT: 0x10000B)
DB23 0 DITHER MAGNITUDE DB22 DB21 DITH1 DITH0 DITHER DITHER RESTART VALUE ENABLE DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DEN DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 CONTROL BITS DB7 DB6 DB5 DV4 DV3 DV2 DB4 DB3 DB2 DB1 DB0 DV1 DV0 C3(0) C2(1) C1(1)
DITH1 0 0 1 1
DITH0 0 1 0 1
DITHER MAGNITUDE 15 (DEFAULT) 7 3 1 (RECOMMENDED) DEN 0 1 DITHER ENABLE DISABLE (RECOMMENDED) ENABLE (DEFAULT) DITHER RESTART VALUE 0x00001 (DEFAULT) ... ... 0x1FFFF
DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1
DV8 0 ... ... 1
DV7 0 ... ... 1
DV6 0 ... ... 1
DV5 0 ... ... 1
DV4 0 ... ... 1
DV3 0 ... ... 1
DV2 0 ... ... 1
DV1 0 ... ... 1
DV0 1 ... ... 1
Figure 16. Register 3--- Modulator Dither Control Register Map
Rev. 0 | Page 12 of 24
ADRF6602
REGISTER 4--PLL CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL (DEFAULT: 0x0AA7E4)
REF OUPUT MUX SELECT DB23 DB22 INPUT REF PATH
CP CURRENT REF SOURCE
PFD POL DB17
PFD PHASE OFFSET MULTIPLIER
CP CURRENT
CP SRC
CP CONTROL DB8 DB7
PFD EDGE DB6 DB5 PE0
PFD ANTI BACKLASH DELAY DB4 DB3
CONTROL BITS DB2 DB1 C2(0) DB0 C1(0)
DB21 DB20 DB19 RS1 RS0
DB18 CPM
DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
RMS2 RMS1 RMS0
CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPCT1 CPCT0 PE1
PAB1 PAB0 C3(1)
PAB0 PAB1 PFD ANTI BACKLASH DELAY 0 0 1 1 PE0 0 1 PE1 0 1 0 1 0 1 0ns (DEFAULT) 0.5ns 0.75ns 0.9ns
REFERENCE PATH EDGE SENSITIVITY FALLING EDGE RISING EDGE (DEFAULT)
DIVIDER PATH EDGE SENSITIVITY FALLING EDGE RISING EDGE (DEFAULT)
CPC1 CPC0 CHARGE PUMP CONTROL 0 0 1 1 CPS 0 1 0 1 0 1 BOTH ON PUMP DOWN PUMP UP TRISTATE (DEFAULT)
CHARGE PUMP CONTROL SOURCE CONTROL BASED ON STATE OF DB7/DB8 (CP CONTROL) CONTROL FROM PFD (DEFAULT)
CPP1 CPP0 CHARGE PUMP CURRENT 0 0 1 1 CPB4 CPB3 CPB2 CPB1 CPB0 0 0 0 0 1 1 CPBD 0 1 CPM 0 1 RS0 0 0 1 1 RS1 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 1 250A 500A (DEFAULT) 750A 1000A
PFD PHASE OFFSET MULTIPLIER 0 x 22.5/ICPMULT 1 x 22.5/ICPMULT 4 x 22.5/ICPMULT (RECOMMENDED) 10 x 22.5/ICPMULT (DEFAULT) 16 x 22.5/ICPMULT 31 x 22.5/ICPMULT
PFD PHASE OFFSET POLARITY NEGATIVE POSITIVE (DEFAULT)
CHARGE PUMP CURRENT REFERENCE SOURCE INTERNAL (DEFAULT) EXTERNAL
INPUT REFERENCE PATH SOURCE 2x REFIN REFIN (DEFAULT) 0.5x REFIN 0.25x REFIN
RMS2 RMS1 RMS0 REF OUTPUT MUX SELECT 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 LOCK DETECT (DEFAULT) VPTAT REFIN (BUFFERED) 0.5x REFIN (BUFFERED) 2x REFIN (BUFFERED) TRISTATE 0.25x REFIN (BUFFERED) DGND
Figure 17. Register 4--PLL Charge Pump, PFD, and Reference Path Control Register Map
Rev. 0 | Page 13 of 24
08545-008
ADRF6602
REGISTER 5--PLL ENABLE AND LO PATH CONTROL (DEFAULT: 0x0000E5)
RESERVED CAP DAC RES DB7 0 PLL EN DB6 PLEN LO DIV1 DB5 LDV1 LO EXT DB4 LXL LO DRV DB3 CONTROL BITS DB2 DB1 DB0
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 0 0 0 0 0 0 0 0 0 0 0 0 CD3 CD2 CD1 CD0
LDRV C3(1) C2(0) C1(1)
CD3 0 1
CD2 0 1
CD1 0 1
CD0 0 1
CAPACITOR DAC CONTROL FOR IIP3 OPTIMIZATION MIN MAX LXL 0 1 LDV1 0 1 PLEN 0 1
LDRV 0 1
LO OUTPUT DRIVER ENABLE DRIVER OFF (DEFAULT) DRIVER ON
EXTERNAL LO DRIVE ENABLE (PIN 37, PIN 38) INTERNAL LO OUTPUT (DEFAULT) EXTERNAL LO INPUT
DIVIDE-BY-2 IN LO CHAIN ENABLE DIVIDE BY 1 DIVIDE BY 2 (DEFAULT)
PLL ENABLE DISABLE ENABLE (DEFAULT)
08545-009
Figure 18. Register 5--PLL Enable and LO Path Control Register Map
REGISTER 6--VCO CONTROL AND VCO ENABLE (DEFAULT: 0x1E2106)
RESERVED DB23 DB22 DB21 0 0 0 CHARGE 3.3V VCO LDO VCO VCO PUMP LDO ENABLE ENABLE ENABLE ENABLE SWITCH DB20 CPEN DB19 L3EN DB18 LVEN VCO AMPLITUDE VCO BW SW CTRL VCO BAND SELECT FROM SPI CONTROL BITS
DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VCO EN VCO SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)
CPEN CHARGE PUMP ENABLE 0 1 DISABLE ENABLE (DEFAULT) L3EN 3.3V LDO ENABLE 0 1 DISABLE ENABLE (DEFAULT) LVEN 0 1 VCO LDO ENABLE DISABLE ENABLE (DEFAULT) VCO EN 0 1 VCO SW 0 1
VC[5:0] 0x00 .... 0x18 .... 0x2B .... 0x3F
VCO AMPLITUDE 0 .... 24 (DEFAULT) .... 43 (RECOMMENDED) .... 63
VBS[5:0] 0x00 0x01 .... 0x3F
VCO BAND SELECT FROM SPI DEFAULT 0x20
VBSRC VCO BW CAL AND SW SOURCE CONTROL 0 1 BAND CAL (DEFAULT) SPI
VCO SWITCH CONTROL FROM SPI REGULAR (DEFAULT) BAND CAL
VCO ENABLE DISABLE ENABLE (DEFAULT)
08545-010
Figure 19. Register 6--VCO Control and VCO Enable Register Map
REGISTER 7--MIXER BIAS ENABLE AND EXTERNAL VCO ENABLE (DEFAULT: 0x000007)
RES MIXER XVCO B_EN RESERVED DB7 DB6 DB5 0 0 0 CONTROL BITS DB4 DB3 DB2 DB1 DB0 0 0 C3(1) C2(1) C1(1) DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 0 XVCO MBE 0 0 0 0 0 0 0 0 0 0 0 0 0 MBE MIXER BIAS ENABLE DISABLE 0 ENABLE (DEFAULT) 1 XVCO 0 1 EXTERNAL VCO INTERNAL VCO (DEFAULT) EXTERNAL VCO
Figure 20. Register 7--Mixer Bias Enable and External VCO Enable Register Map
Rev. 0 | Page 14 of 24
08545-011
ADRF6602 THEORY OF OPERATION
The ADRF6602 integrates a high performance downconverting mixer with a state-of-the-art fractional-N PLL. The PLL also integrates a low noise VCO. The SPI port allows the user to control the fractional-N PLL functions and the mixer optimization functions, as well as allowing for an externally applied LO or VCO. The mixer core within the ADRF6602 is the next generation of an industry leading family of mixers from Analog Devices, Inc. The RF input is converted to a current and then mixed down to IF using high performance NPN transistors. The mixer output currents are transformed to a differential output. The high performance active mixer core results in an exceptional IIP3 and IP1dB, with a very low output noise floor for excellent dynamic range. Over the specified frequency range, the ADRF6602 typically provides IF input P1dB of 14.5 dBm and IIP3 of 30 dBm. Improved performance at specific frequencies can be achieved with the use of the internal capacitor DAC (CDAC), which is programmable via the SPI port, and through the use of a resistor to a +5 V supply from the IP3SET pin (Pin 29). Adjustment of the capacitor DAC allows increments in phase shift at internal nodes in the ADRF6602, thus allowing cancellation of thirdorder distortion with no change in supply current. Connecting a resistor to a +5 V supply from the IP3SET pin increases the internal mixer core current, thereby improving overall IIP2 and IIP3, as well as IP1dB. Using the IP3SET pin for this purpose increases the overall supply current. The fractional divide function of the PLL allows the frequency multiplication value from REF_IN to LO output to be a fractional value rather than be restricted to an integer value as in traditional PLLs. In operation, this multiplication value is INT + (FRAC/MOD), where INT is the integer value, FRAC is the fractional value, and MOD is the modulus value, all programmable via the SPI port. In other fractional-N PLL designs, fractional multiplication is achieved by periodically changing the fractional value in a deterministic way. The disadvantage of this approach is often spurious components close to the fundamental signal. In the ADRF6602, a - modulator is used to distribute the fractional value randomly, thus significantly reducing the spurious content due to the fractional function.
Table 7. ADRF6602 Register Functions
Register Register 0 Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Function Integer divide control for the PLL Modulus divide control for the PLL Fractional divide control for the PLL - modulator dither control PLL charge pump, PFD, reference path control PLL enable and LO path control VCO control and VCO enable Mixer bias enable and external VCO enable
Note that internal calibration for the PLL must be run when the ADRF6602 is initialized at a given frequency. This calibration is run automatically whenever Register 0, Register 1, or Register 2 is programmed. Because the other registers affect PLL performance, Register 0, Register 1, and Register 2 should always be programmed last and in this order: Register 0, Register 1, Register 2. To program the frequency of the ADRF6602, the user typically programs only Register 0, Register 1, and Register 2. However, if registers other than these are programmed first, a short delay should be inserted before programming Register 0. This delay ensures that the VCO band calibration has sufficient time to complete before the final band calibration for Register 0 is initiated. Software is available on the product page of the Analog Devices website (www.analog.com) that allows easy programming from a PC running Windows XP or Vista.
INITIALIZATION SEQUENCE
To ensure proper power-up of the ADRF6602, it is important to reset the PLL circuitry after the VCC supply rail settles to 5 V 0.25 V. Resetting the PLL ensures that the internal bias cells are properly configured, even under poor supply start-up conditions. To ensure that the PLL is reset after power-up, follow this procedure: 1. 2. 3. Disable the PLL by setting the PLEN bit to 0 (Register 5, Bit DB6). Disable the VCO LDO internal node by setting the LVEN bit to 0 (Register 6, Bit DB18). After a delay of >100 ms, set the PLEN and LVEN bits to 1.
PROGRAMMING THE ADRF6602
The ADRF6602 is programmed via a 3-pin SPI port. The timing requirements for the SPI port are shown in Figure 2. Eight programmable registers, each with 24 bits, control the operation of the device. The register functions are listed in Table 7.
After this procedure, the other registers can be programmed, in order, from Register 7 to Register 3, and then from Register 0 to Register 2, as described in the Programming the ADRF6602 section.
Rev. 0 | Page 15 of 24
ADRF6602
LO SELECTION LOGIC
The downconverting mixer in the ADRF6602 can be used without the internal PLL by applying an external differential LO to Pin 37 and Pin 38 (LON and LOP). In addition, when using an LO generated by the internal PLL, the LO signal can be accessed directly at these same pins. This function can be used for debugging purposes, or the internally generated LO can be used as the LO for a separate mixer.
Table 8. LO Selection Logic
Pin 16 (PLL_EN) 0 0 1 1 1 1
1
The operation of the LO generation and whether LOP and LON are inputs or outputs are determined by the logic levels applied at Pin 16 (PLL_EN) and Pin 36 (LODRV_EN), as well as Bit DB3 (LDRV) and Bit DB6 (PLEN) in Register 5. The combination of externally applied logic and internal bits required for particular LO functions is given in Table 8.
Pins1 Pin 36 (LODRV_EN) X X X 0 X 1
Register 5 Bits1 Bit DB6 (PLEN) Bit DB3 (LDRV) 0 X 1 X 0 X 1 0 1 1 1 X
Output Buffer Disabled Disabled Disabled Disabled Enabled Enabled
Outputs LO External External External Internal Internal Internal
X = don't care.
Rev. 0 | Page 16 of 24
ADRF6602 APPLICATIONS INFORMATION
BASIC CONNECTIONS FOR OPERATION
Figure 21 shows the schematic for the ADRF6602 evaluation board. The six power supply pins should be individually decoupled using 100 pF and 0.1 F capacitors located as close as possible to the device. In addition, the internal decoupling nodes (DECL3P3, DECL2P5, and DECLVCO) should be decoupled with the capacitor values shown in Figure 21. The RF input is internally ac-coupled and needs no external bias. The IF outputs are open collector, and a bias inductor is required from these outputs to VCC. A peak-to-peak differential swing on RFIN of 1 V (0.353 V rms for a sine wave input) results in an IF output power of 3.8 dBm. The reference frequency for the PLL should be from 12 MHz to 160 MHz and should be applied to the REF_IN pin, which should be ac-coupled and terminated with a 50 resistor as
VCC R43 10k (0402) S2 VCC RED +5V C7 0.1F (0402) VCC1 RED R39 OPEN (0402) S1 OPEN R40 0 (0402) LO IN/OUT R41 0 (0402) 4 5 3 1 R6 0 (0402) C8 100pF (0402) VCC_LO
34
shown in Figure 21. The reference signal, or a divided-down version of the reference signal, can be brought back off chip at the multiplexer output pin (MUXOUT). A lock detect signal and a voltage proportional to the ambient temperature can also be selected on the multiplexer output pin. The loop filter is connected between the CP and VTUNE pins. When connected in this way, the internal VCO is operational. For information about the loop filter components, see the Evaluation Board Configuration Options section. Operation with an external VCO is also possible. In this case, the loop filter components should be referred to ground. The output of the loop filter is connected to the input voltage pin of the external VCO. The output of the VCO is brought back into the device on the LOP and LON pins, using a balun if necessary.
P1 9-PIN DSUB
1
2
3
4
5
6
7
8
9
R19 0 R20 (0402) 0 (0402)
R35 0 (0402)
R36 0 R30 (0402) 0 (0402) R48 0 (0402) C31 OPEN (0402) C32 OPEN (0402) C30 OPEN (0402) R44 OPEN (0402) R45 OPEN (0402) R42 OPEN (0402)
R47 10k (0402)
C27 0.1F (0402) R27 0 (0402) C26 100pF (0402) VCC_MIX
22
C25 0.1F (0402) R26 0 (0402) C24 100pF (0402) VCC_LO
17
C23 0.1F (0402) R25 0 (0402) C22 100pF (0402) VCC2
10
C20 0.1F (0402) R24 0 (0402) C21 100pF (0402) VCC1
1
C19 0.1F (0402) R17 0 (0402) C18 100pF (0402)
PLL_EN
DATA
12
CLK
VCC_V2I
27
16
13
LE
14 9
DECL2P5 C16 R18 100pF 0 (0402) (0402) DECL3P3 C12 R8 100pF 0 (0402) (0402) C11 0.1F (0402) C41 OPEN (0603) C17 0.1F (0402) C42 10F (0603)
LODRV_EN LON
36 37 BUFFER
SPI INTERFACE DIVIDER /2 2:1 MUX DIV BY 4, 2, 1
26 2
C5 1nF LOP 38 (0402) FRACTION REG MODULUS INTEGER REG
T8 TC1-1-13+ C6 1nF (0402) C13 1nF (0402) REF_IN
BUFFER
ADRF6602
THIRD-ORDER FRACTIONAL INTERPOLATOR x2
6
RFIN R22 0 (0402) IP3SET R27 0 (0402)
RFIN
REF_IN R73 49.9 (0402) REFOUT
N COUNTER 21 TO 123 MUX TEMP SENSOR
4 7
PRESCALER /2 CHARGE PUMP 250A, 500A (DEFAULT), 750A, 1000A
VCO CORE
/2 /4 MUXOUT
8
- PHASE + FREQUENCY DETECTOR
29
C27 0.1F (0402)
R16 0 (0402)
11 15 20 21 23 24 25 28 30 31 35
RSET R2 R37 OPEN 0 (0402) (0402)
5
3
39
40
18
19
CP
VTUNE DECLVCO R62 0 (0402)
IFP VCC +5V
IFN
1 2
4
RFOUT R43 0 (0402)
CP TEST POINT (ORANGE)
R38 0 (0402)
R9 18k R65 0 (0402) (0402) R10 1.6k (0603) C15 5.6nF (1206) R11 OPEN (0402)
VTUNE R63 OPEN (0402)
R27 0 3 (0402) C29 0.1F (0402)
5
C14 270pF (0603)
C13 27pF (0603)
C40 OPEN (0603) R12 0 (0402)
R1 0 (0402) C1 100pF (0402)
Figure 21. Basic Connections for Operation of the ADRF6602
Rev. 0 | Page 17 of 24
08545-024
C43 10F (0603)
C2 OPEN (0402)
ADRF6602 EVALUATION BOARD
Figure 24 shows the schematic of the RoHS-compliant evaluation board for the ADRF6602. This board has four layers and was designed using Rogers 4350 hybrid material to minimize high frequency losses. FR4 material is also adequate if the design can accept the slightly higher trace loss of this material. The evaluation board is designed to operate using the internal VCO of the device (the default configuration) or with an external VCO. To use an external VCO, R62 and R12 should be removed. Place 0 resistors in R63 and R11. The input of the external VCO should be connected to the VTUNE SMA connector, and the external VCO output should be connected to the LO IN/OUT SMA connector. In addition to these hardware changes, internal register settings must also be changed to enable operation with an external VCO (see the Register 6-- VCO Control and VCO Enable (Default: 0x1E2106) section). Additional configuration options for the evaluation board are described in Table 9.
EVALUATION BOARD CONTROL SOFTWARE
Software to program the ADRF6602 is available for download from www.analog.com. To install the software, download and extract the zip file. Then run the following installation file: ADRF6x0x_3p0p0_XP_install.exe The evaluation board can be connected to the PC using a PC parallel port or a USB port. These options are selectable from the opening menu of the software interface (see Figure 22). The evaluation board is shipped with a 25-pin parallel port cable for connection to the PC parallel port. To connect the evaluation board to a USB port, a USB adapter board (Part No. EVAL-ADF4XXXZ-USB) must be purchased from www.analog.com. This board connects to the PC using a standard USB cable with USB mini-connector at one end. An additional 25-pin male to 9-pin female adapter is required to mate the ADF4XXXZ-USB board to the 9-pin D-Sub connector on the ADRF6602 evaluation board.
Figure 22. Control Software Opening Menu
Figure 23 shows the main menu of the control software with the default settings displayed.
Rev. 0 | Page 18 of 24
08545-025
ADRF6602
Figure 23. Main Screen of the ADRF6602 Evaluation Board Software
Rev. 0 | Page 19 of 24
08545-026
T7 P1-T7 1 1A 2
AG N D AG N D
6 6A 5 5A 4 4A P4-T7 P4-T7
P1-T7
2A P3-T7 3 3A VCC P3-T7 GND GND1 1 1 GND2 1 1 VCC
VCC _RF
VCC _LO
VCC _BB
ADRF6602
0
R29
0 R31
R32 0
T8
AGN D AG N D
P4-T7 P3-T7 P1-T7 0 NC P1-6
AG N D
1 5 R69 LO 4 2 3
SNS1 VCC _SENSE SNS
10UF
C28
AG ND
VTUNE LO_EXTERN VCC _LO R6 VCC _LO 0 1 100 PF 0
AG ND AG ND
R72 0
1
AG ND
R63 100 K C8 0.1UF R68 OUTPUT_EN 0 DNI C7
SCHEMATICS AND ARTWORK
VCO_LDO LO_EXTERN 2P5V_LDO
J1 10 J1 9 J1 8 J1 7
R38 1K 0
R9
R65
CP
R10
806
C14
1NF
1NF
0
0
R33 0
C6
C5
R37
R62
1000 PF C15 1 VCC IP3SET 0 R67 0.022 UF
C13 470 PF C40 TBD VCC 1
R66
0
3P3V_LDO
J1 6 J1 5 AGND VCC _SENSE AGND J1 4 J1 3 J1 2 VCC J1 1
VCC 4 R55 10K
3
1 R56 10K
2
VCC
R7
R11 DNI
0
R12 0
C9 C10
AG N D AGN D
S1
VCO _LDO VCO _LDO R1 1 IP3SET
AG ND
0.1UF 100 PF
AG N D
AG N D
1
1 R27 0
IP3SET OUT VCC _BB TBD C27 0.1UF
AG N D AG ND AG ND
3P3V1 R49 C2 0.1UF
AG ND AG ND
1 C1 100 PF 40 39 38 37 36 35 34 33 32 31 R60 TBD 0 DNI C12
R8
3P3V_LDO
C41
C11
NC
LOP
LON
GND
NC
AG ND
AG N D
AG N D
VCC _LO
DECLVCO
LODRV_EN
10UF
AG N D
VTUNE
GND
VCC _RF
AG ND
4
1 IP3SET GND VCC _V2I Z1 RFIN GND GND GND VCC _MIX GND 28 27 3 CP 4 GND R2
AG ND
R15
2 DECL3P3
29 C24 100 PF
AG N D
VCC _RF 0 C25 0.1UF
AG ND
OSC_3P3V
1
2
C4 5R SET 6 REF_IN
26 25 24 23 R25 22 21 C22 100 PF E-PAD PAD 0 VCC _BB1 1 VCC _BB
AGN D
Y1
R14
DNI
R71
TBD
GND
DATA
CL K
LE
GND
PLL_EN
VCC _LO
IFP
IFN
R70 49.9 R16 0 11 13 2P5V 12 14
GND
1
0.1UF 1 2 3 VCC 2 5 R17 0 C19 0.1UF
AG ND AG ND
100 PF P1-1
AG ND
R19 0 DATA R30 0 R58 DNI
R35
C42 10UF C17 P1
AG N D
0
1
R20
0 R34
1 6 7 C18 100 PF 8 9 VCC
0
LE
VCC 5
08545-023
100 DNI PF
AG N D
Figure 24. Evaluation Board Schematic
100 PF C43
AG ND
22000 F P C3 DNI 7 GND 8 MUXOUT P1-1
AG N D
R28 0
RFIN
10PF
AG ND
C29 0.1UF
3
TC4-1W
T3 R59 0
AG ND
Rev. 0 | Page 20 of 24
1 VCC1 GND 30 9 DECL2P5 10 VCC2 REFOUT
AG N D AG N D
0
REFIN
C31
6
C23 0.1UF
AG N D
OSC_3P3V
R26
1
R43
0
10UF
0.1UF
VCC
1000 PF
AG ND
15
16
17
18
19
20
C35 IFP DNI
AG ND
1
AG N D
CLK R18 C32 100 DNI PF 0 C16 R50 1K DNI
2P5V_LDO
VCC
AG ND
L1 TBD R47 0
AG N D
R44 DNI
AG ND AG ND
4
R48 VCC _LO1 P1-6 R57 R36 0 0 1
AG N D
VCC L2 R24 0 C21 C20 1 TBD DNI VCC _LO C36
0 IFN
AMP745781 -4
DIG_GND
AG N D
100 PF
1
AG ND
0.1UF
AGN D
R51 1K DNI
C33 100 DNI PF
S2
2
3
OUTPUT_EN
AG ND
R53 10K R52 1K DNI C34
R54 10K
VCC 1
AG ND
1
ADRF6602
08545-013
Figure 25. Evaluation Board Layout (Bottom)
Figure 26. Evaluation Board Layout (Top)
Rev. 0 | Page 21 of 24
08545-012
ADRF6602
EVALUATION BOARD CONFIGURATION OPTIONS
Table 9.
Component S1, R55, R56, R33 Description LO select. Switch and resistors to ground the LODRV_EN pin. The LODRV_EN pin setting, in combination with internal register settings, determines whether the LOP and LON pins function as inputs or outputs (see the LO Selection Logic section for more information). LO input/output. An external 1x LO or 2x LO can be applied to this single-ended input connector. Reference input. The input reference frequency for the PLL is applied to this connector. Input impedance is 50 . Multiplexer output. The REFOUT connector connects directly to the MUXOUT pin. The on-board multiplexer can be programmed to bring out the following signals: REFIN, 2x REFIN, REFIN/2, REFIN/4. Temperature sensor output voltage. Lock detect indicator. Charge pump test point. The unfiltered charge pump signal can be probed at this test point. Note that the CP pin should not be probed during critical measurements such as phase noise. Loop filter. Loop filter components. Loop filter return. When the internal VCO is used, the loop filter components should be returned to Pin 40 (DECLVCO) by installing a 0 resistor in R12. When an external VCO is used, the loop filter components can be returned to ground by installing a 0 resistor in R11. Internal vs. external VCO. When the internal VCO is enabled, the loop filter components are connected directly to the VTUNE pin (Pin 39) by installing a 0 resistor in R62. To use an external VCO, R62 should be left open. A 0 resistor should be installed in R63, and the voltage input of the VCO should be connected to the VTUNE SMA connector. The output of the VCO is brought back into the PLL via the LO IN/OUT SMA connector. RSET pin. This pin is unused and should be left open. RF input. The RF input signal should be applied to the RFIN SMA connector. The RF input of the ADRF6602 is ac-coupled, so no bias is necessary. IF output. The differential IF output signals from the ADRF6602 (IFP and IFN) are converted to a single-ended signal by T3. Default Condition/ Option Settings S1 = R55 = open (not installed) R56 = R33 = 0 LODRV_EN = 0 V LO input
LO IN/OUT SMA Connector REFIN SMA Connector REFOUT SMA Connector
Lock detect
CP Test Point
R37, C14, R9, R10, C15, C13, R65, C40 R11, R12
R12 = 0 (0402) R11 = open (0402) R62 = 0 (0402) R63 = open (0402)
R62, R63, VTUNE SMA Connector
R2 RFIN SMA Connector T3
R2 = open (0402) R3 = R23 = open (0402)
Rev. 0 | Page 22 of 24
ADRF6602 OUTLINE DIMENSIONS
6.00 BSC SQ 0.60 MAX
31 30 40 1
0.60 MAX PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
5.75 BSC SQ
0.50 BSC 0.50 0.40 0.30
EXPOSED PAD
(BOT TOM VIEW)
4.25 4.10 SQ 3.95
10
21 20
11
0.25 MIN 4.50 REF
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 27. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm x 6 mm Body, Very Thin Quad (CP-40-1) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 ADRF6602ACPZ-R7 ADRF6602-EVALZ
1
Temperature Range -40C to +85C
Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
072108-A
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
Package Option CP-40-1
Z = RoHS Compliant Part.
Rev. 0 | Page 23 of 24
ADRF6602 NOTES
(c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08545-0-1/10(0)
Rev. 0 | Page 24 of 24

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